Artificial Intelligence/Machine Learning,
Asynchronous Neuromorphic Digital Readout Circuit for Infrared Cameras for Autonomous Target Acquisition and Autonomous Vehicles
Release Date: 11/16/2021
Open Date: 11/30/2021
Application Due Date: 01/04/2022
Close Date: 01/04/2022
Topic Number: A214-051
Duration: Up to 6 months
Amount Up To: $250K
Most military scenarios consist of highly cluttered and dynamic scenes. Asynchronous on chip smart event cameras can eliminate cluttered scenarios with a much-reduced latency, power, and would be able to hand off images of interest to imbedded autonomous target algorithms. Development of a smart digital readout circuit, with embedded processing, containing this capability would significantly enhance infrared cameras for use in autonomous detection. The objective of this topic is to take this new technology and apply it to the 3GEN FLIR program and all other systems that use or will use 3GEN FLIR Cameras.
Currently, 3GEN FLIR consists of imaging in two infrared bands with four fields of view. This capability for the Army increases the effectiveness of the sensors to operate in all atmospheric conditions with much longer range than previous versions. In addition, new ground systems will employ autonomous vehicles that will have to contain some use of artificial intelligence to navigate and target. This will regain overmatch by reducing target acquisition time and engagement timelines compared to today’s manual search and acquiring “next target” process. It will also reduce the cognitive burden for vehicle crew by automating search and acquisition – targets are verified by man-in-the-loop prior to engagement. The project, if successful, will make a game changing improvement by indicating temporal events at the focal plane level and reduce latency of target acquisition times. This project will design a neuromorphic chip to be combined with the digital 3GEN FLIR readout circuit at the 12 micron pixel level. This two chip stacked readout will perform the basic sensor functions as well as the neuromorphic processing. Power dissipation of the neuromorphic chip will be at a minimum since it is cryogenically cooled to 75K and added heat load needs to be minimized.
Phase I will be a short study phase to come up with a neuromorphic design chip.
Phase II will consist of the design and fabrication of the asynchronous neuromorphic digital readout. Testing will be done to prove out the concept performance. If Phase II Sequential required, it should demonstrate the chip in a 3GEN FLIR focal plane. Packaging and testing will validate the conceptual success of the project.
Phase III will consist of the commercialization of the selected proposal.
For more information, and to submit your full proposal package, visit the DSIP Portal.
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